Teaport UART
This page describes the Teaport UART, a GNU GPL version 3 licensed IP core that was originally designed by myself for the FX12 virtual lab embedded system. Two components are distributed on this page:
- An IP core, in a format which is recognised by Xilinx Platform Studio (also known as EDK). The IP core interfaces to a PLBv46 bus, currently standard in EDK. (GPL version 3 licence.)
- A Linux kernel driver for the component. (GPL version 2 or 3 licence.)
The Teaport hardware is copyright (C) Jack Whitham 2009 and portions are (C) Martin Schoeberl 2008. See acknowledgement.
Why Teaport?
A UART sends and receives data via a serial line. EDK already provides two choices of UART, including a 16550A-compatible design, but neither is suitable for the virtual lab because the maximum data rate is too low. The 16550A design has room for at most 16 bytes in its internal FIFO. The operating system must regularly remove bytes from the UART, or the FIFO will overflow and data will be lost.
At first, the 16550A design was perfectly adequate for the virtual lab, where the serial links operated at a fairly low speed (115200 bits per second). But data loss problems appeared when more than one serial line was in use at the same time, causing connections to break. I traced this problem to the UART. At the time, we were using Linux on a pair of Pentium-II PCs as the virtual lab embedded system, and the 16550A UARTs on the Pentium-II motherboards were losing data as their FIFOs overflowed. An identical problem was seen with the Xilinx 16550A design. Flow control is the usual solution, but many FPGA boards do not support hardware flow control because the relevant control lines are omitted. Software flow control could be used but this would complicate the FPGA design.
The Teaport UART is my solution to the issues. Teaport uses an FPGA block RAM to provide 1023 byte FIFOs for sending and receiving data. It also allows the software to receive up to three bytes in a single bus transaction, whereas the 16550A design requires two bus transactions per byte. These decisions make Teaport reliable in situations where two, three or four serial lines are all active at high speeds.
Many 16550A features are not present in Teaport. For example, Teaport only supports the most common serial setting of "8 bits, no parity, one stop bit". It does not support hardware flow control. It will not record framing errors. If you need these things, then Teaport is not for you.
Acknowledgement
The UART at the core of Teaport is copyrighted by Martin Schoeberl, who designed it as part of his JOP CPU. JOP executes Java code natively and is intended for use in hard real-time embedded systems. I am able to use Martin's VHDL code because he has released it under the GNU GPL version 3, and this is the same license as the rest of the Teaport design.
Hardware Design
The Teaport hardware design is VHDL. It can be imported into EDK version 10.1; other versions are untested. Its hardware connections are identical to those on the Xilinx 16550A design; this deliberate choice allows the Teaport design to act as a drop-in replacement for the 16550A, at least as far as hardware is concerned. (Entirely different software drivers are required.) Most of the wires are not used, because Teaport does not have support for many of the features of the 16650A.
- teaport_v1_00_a.tar.gz - Xilinx Platform Studio component.
Software Driver
A software driver exists for Linux. The software driver includes modifications to the "open firmware" subsystem. Open firmware is used by Xilinx software to inform Linux about the locations of hardware devices using "gen-mhs-devtree". There is no generic way to specify a serial device and driver, so the open firmware subsystem is patched to include Teaport in its list of options.
- teaport_v1_00_sw.tar.gz - Linux kernel driver files for Teaport.