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These web pages provide the user manual and design documents for Virtual Lab II (VL2), the second generation of the remote FPGA development system. The purpose of the system is to provide a centralised shared resource for all experiments that use FPGAs. The system was designed and built within the Department of Computer Science at University of York. The design goals of VL2 are documented.

The following map shows all of the components in a typical VL2 system. You can click on the components to reach associated documentation. If you want to use VL2, you might want to skip to the User Guide. Some of the components can be downloaded. There is a complete sample application in addition to a number of shorter sample programs.

Virtual Lab Map

vlab protocol over SSH vlabif protocol over serial link Debugging Module Debugging Hardware Virtual Lab Interface Hardware Module Private Key Authentication Virtual Lab Interface Hardware FX12 Monitor FPGA PPC Linux Board Server Mutual Exclusion Server Relay Shell Virtual Lab Module

Architecture Overview

The image above shows the architecture of VL2. As in VL1, a relay server (running the relay shell) acts as the head of the service, connecting users (clients) to FPGA boards and enforcing a security policy. In VL2, the security policy is enforced by SSH authentication in place of PHP. (It was possible to bypass VL1 security by connecting directly to a TCP/IP port: this is not possible in VL2.) The relay shell also logs commands and FPGA bitfiles.

On the user's side of the relay server, the communication is normally carried out via the vlab module (a code library written in Python) although it is also possible to connect directly to the relay service using SSH software and operate it in a sort of "console mode". This was not possible in VL1 because (1) the protocol was binary and (2) a timeout would occur after a few seconds of inactivity.

On the lab side of the relay server, an embedded system called the board server provides all services that are local to a single board. These services are documented in the vlab protocol documentation.

The minimal bus between the FPGA and the board interface is designed to avoid the problems encountered with VL1's bus, which was (a) application-specific, (b) very wide (and hence difficult to connect to new FPGAs), and (c) required custom driver hardware at both ends. We use a simple and well-known standard for communication: RS232. Activating the appropriate service links the FPGA serial port to the user program, so the user program can interact with programs on the FPGA. This could be used for debugging, software downloads, a user interface, or as a signal carrier for a VL1-style interface.

List of Components

VL2 is actually implemented as seven distinct components. These are:

  Copyright (C) Jack Whitham 1997-2011